Electronic designs may be large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing electronic designs, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of electronic design automation (EDA) tools to manage and optimize designs. EDA tools perform the time-consuming tasks of synthesis, placement, and routing. Some EDA tools allow users to specify long-path timing constraints such as, for example, FMAX (maximum clocking frequency), TSU (setup time), and TCO (clock-to-output time), in order for designs to meet performance targets. Only recently have EDA tools taken into account short-path timing constraints.
Current FPGA architectures do not offer features specifically designed to improve the efficiency and effectiveness of short-path timing optimization in EDA tools. Consequently, it is difficult to add the right amount of delay to solve short-path timing constraints in the presence of other constraints of a system. For example, in order to add delay, wires are often wasted because routing patterns on an FPGA do not support a more efficient solution. In some instances, the appropriate delay within legal delay bounds may also not be achievable because the routing patterns on the FPGA may only support routes that have too little delay (causing a short-path timing violation) or too much delay (causing a long-path timing violation).
Thus, what is needed is a method and apparatus for facilitating the efficient and effective optimization of short-path timing constraints.